Semiconductor manufacturers who make integrated circuit chips begin by manufacturing semiconductor wafers. Each wafer is typically 100 mm, 125 mm, 150 mm, 200 mm or 300 mm in diameter and contains anywhere from one to several thousand chips or die on the wafer. When manufacture of the wafer is completed, chips or die are cut or “diced” from the wafer and may later be mounted into single chip or multiple chip packages for implementation in a printed circuit board or other applications.
When manufacture of a wafer is completed, and before the chips or die are cut or “diced” from the wafer, it is customary practice to test each chip on the wafer to determine whether each chip, as manufactured, electrically matches design criteria, matches performance criteria of the system in which the chip is to be implemented, and will be reliable in operation. If a chip fails electrical testing or reliability testing, the chip is not suitable for implementation in a system without repairing the chip or exercising redundancy features which may have been designed into the chip. Performance testing of chips may be used to speed sort chips into different categories suitable for different applications.
Reliability testing is used to screen out chips having an undesirable short life span. Typically, a significant percentage of a group of chips will fail early in their lifetime due to marginal conditions during manufacture. Subsequently, a very low percentage of the group will fail during an extended period of use of the chips. Reliability testing of semiconductor chips is typically performed by a process of supplying test signal patterns to chips under test to repeatedly stimulate all devices and wires on a chip. It is typically performed at elevated temperatures to simulate the first six months of operation. The testing procedure is known as burn-in.
Burn-in is typically performed on integrated circuits at temperatures between 90 degrees C. to 125 degrees C., for a time of up to about 150 hours.
US Patent Application Publication No. 2005/0014301, submitted by Hamren et al, published Jan. 20, 2005, relates to an improved method and apparatus for the handling and testing of semiconductor devices. Semiconductor dice are temporarily attached to a die carrier to enable testing of the dice with conventional technology. In one embodiment, the die carrier comprises a flex circuit base substrate and a rigid support frame. A temporary electrical connection is made with the semiconductor dice during testing. Materials for making the electrical connection are selected from the group consisting of a conductive film, a conductive tape, a conductive epoxy resin, and other adhesives containing a conductive filler.
WO 00/31784, published on Jun. 2, 2000, relates to the use of a sacrificial support to allow selective etching of a wafer having a semiconductor active device layer on one surface of the layer. The sacrificial support is bonded to one surface of the wafer, and provides structural integrity to the transistor device layer. The sacrificial support is removed after formation of a heat conductive layer. By use of the sacrificial support as a mechanical handling means, a thin active device layer can be formed and processed.
None of the above references, taken either separately or in combination, serve to anticipate the present invention as herein disclosed and claimed.